An Integrated Hardware-Software Approach to Transactional Memory

Transactional memory has been proposed as a general and flexible way to allow programs to read and modify disparate primary-memory locations atomically as a single operation, much as a database transaction can atomically modify many records on disk. Hardware transactional memory supports atomicity through architectural means, whereas software transactional memory supports atomicity through languages, compilers, and libraries. Hardware transactional memory can be implemented quite easily with some modificaitons to the processor cache and cache controllers. However, this implementation imposes limitations on the size and length of transactions. On the other hand, software transactional memory does not suffer from these limitations but has a much higher overhead than hardware transactions. In this paper, I propose an integrated hardware-software implementation of transactional memory. The integrated approach gives us the best of both hardware and software transactions. It allows small and short transactions to run in hardware with very low overhead. In the common case, transactions are small and short so it is desirable to run them fast. On the other hand, large and long transactions run slower in software but are nevertheless possible and fully supported. Moreover, the high overhead is also amortized over the common case and thus does not have a significant penalty on overall performance.